Field of the Invention
This invention relates generally to integrated circuits and bipolar transistors formed therein, and relates more particularly to a structure for a bipolar transistor having its base contact outside the isolation region and having a self-aligned emitter-base spacer thereby reducing the transistor cell size and improving the transistor's electrical characteristics.
Parasitic and inherent capacitances and resistances in integrated circuit structures are the principal limiting factors on switching speed and cutoff frequency. Some of these capacitances and resistances are parasitic, i.e., present only because of the integrated structure of the transistor. Others are inherently present because of the junction nature of a transistor and its peculiar geometry. For example, any transistor has a base spreading resistance caused by the long narrow path of current in the base to the emitter and collector junctions. In addition there is a parasitic resistance caused by the contact structure from the external base terminal to the base region of the transistor in the semiconductor lattice. Further, there is an emitter capacitance and a collector capacitance both of which arise from the presence of PN junctions in the device. The emitter and collector capacitances are the sum of the diffusion capacitances and the space charge capacitances across the emitter-base and base-collector junctions respectively. The areas of these junctions affect the value of these capacitances with larger areas causing larger capacitances. Therefore smaller transistors have smaller parasitic capacitances.
When a high frequency switching waveform is applied across the base-emitter junction of a swtching transistor, the emitter and collector capacitors tend to shunt the high frequency components for which these capacitances represent very low impedances. That is, when the switching waveform changes states, the capacitors tend to act as momentary shorts. When a transistor changes states from off to on or vice versa, the base current causes elimination of excess minority carrier charge stored in the base to cut the transistor off or causes storage of minority carrier charge to drive the transistor into saturation. Because of the low impedances of the emitter and collector junction capacitances, this base current is temporarily shunted therby diverting it from these functions. This diversion of the base current into these capacitors occurs until they are charges up, at which time the base current can commence charge storage or elimination of stored excess minority carrier charge. These charge storage or charge elimination events must occur before the transistor can change states from off to on or vice versa. Because there is no immediate change in state when the input waveform across the base-emitter junction changes state, there is no immediate change in the collector current. The collector current will not change until such time as the parasitic and inherent capacitors charge up and the charge in the base begins to change. This charging or discharging rate of the base is established by the sizes of the various capacitors and by the magnitude of the base spreading resistance through which the charging currents flow. The charging or discharging rate is the principal limitation on the switching speed of the transistor.
To maximize switching speed, the values of the capacitances must be minimized and the base spreading resistance must be kept low to provide a low RC time constant.
Workers in the art have devised processing techniques to yield transistor structures which have lower base spreading resistances than commonly found in prior bipolar transistor structures. Such an advance is described in a co-pending patent application entitled "Self Aligned Silicide Base Contact For A Bipolar Transistor", Ser. No. 629,039, filed Jul. 9, 1984. There the base spreading resistance was reduced by reducing the length of the path which current between the emitter and base had to travel. This reduction in path was caused by use of a self aligned base and emitter contacts of silicide separated by self aligned, thin oxide spacer insulator regions thereby eliminating the clearances between the base and emitter contacts that formarly had to be observed under the design rules for mask alignment tolerances in processes using separate base and emitter masks.
Although this process and structure lowers the base spreading resistance, it does not lower the parasitic and inherent emitter and collector capacitances associated with the integrated transistor structure.
The purpose of the present invention is to reduce the magnitude of parasitic and inherent capacitances associated with the integrated bipolar transistor structures previously known.